The present invention is related to the field of power-on-reset circuits and, more particularly, to power-on-reset circuits having a zero current state while the supply voltage is in a predetermined, valid range that is defined as the state in which the logic circuits are functional, and to integrated circuits having such power-on-reset circuits.
Power-on-reset (POR) circuits are commonly used in connection with digital and mixed-signal systems to initialize all logic elements associated with the integrated circuit to a known state simultaneously as soon as the power supply or supply voltage of the electronic circuit is first applied, e.g., during “power-up”. More specifically, the POR circuit outputs a reset signal to a plurality of logic elements, e.g., latches, flip-flops or other sequential circuits, until a predetermined threshold supply voltage is reached after power-up. By resetting and maintaining a common state on all of the logic elements simultaneously, the POR circuit prevents aberrant behavior of the electronic device, which may lead to failure or inoperability of the device.
Although the functional intricacies and capabilities of electronic devices require greater power, in design, the cost and benefits of greater power consumption must be weighed against, for example, size, weight, cooling requirements, battery life, and the like. Conventionally, when the electronic device is not in use, modern integrated circuit or “chip” design includes a power-down (PD) function to lower power demand and thereby increase battery life. Hence, when the electronic circuits are in a PD mode, the chip is in an OFF state in which all or substantially all of the active circuits on the chip are OFF. By convention, in a PD state, the specified chip current is less than 1 micro-Ampere (μA). In practice, the chip current is in the nano-Ampere (nA) range.
To designers, this creates a troublesome paradox. All POR circuits require at least a small amount of current and/or require external or internal voltage references for power-up in order to function properly and, more particularly, to generate a RESET pulse at power-up. However, in many applications that require low power consumption, the power consumed by always-active POR circuits is problematic.
One possible solution involves providing a PD input for the POR circuit that disables the POR circuit in PD mode, causing the POR circuit to consume zero current in PD mode.
Alternatively, many software-controlled systems activate the POR circuit from a PD mode by storing a PD signal in a memory element, e.g., a latch, flip-flop, control register, and the like. Disadvantageously, the memory element may, by chance, initialize the PD signal active at power-up. Such an occurrence, however, would disable the POR circuit at power-up, inhibiting the POR circuit from generating a RESET signal and, thereby, causing the system to fail to initialize properly.
For example, U.S. Pat. No. 6,710,634 to Ohbayashi, et al. discloses a POR circuit for use on a low-power consumption semiconductor having a low power supply voltage. Ohbayashi's POR circuit includes an inverter that drives the reset signal when the voltage at the input node of the inverter exceeds a threshold voltage. According to the teachings of Ohbayashi, the voltage potential at the input node of the inverter is defined by a voltage divider that consists of a p-type MOS transistor in series with an n-type MOS transistor. Ohbayashi, however, does not address instances in which the POR circuit itself is in a PD state.
As another example, U.S. Pat. No. 6,181,173 to Homol, et al. discloses a POR circuit that generates a reset signal as long as the supply voltage is not in the operational range of the electronic device and, once the supply voltage returns to a nominal value, maintains the reset signal for a period of time. Homol, however, also does not address instances in which the POR circuit itself is in a PD state.
Accordingly, it would be desirable to provide a POR circuit that, by design, consumes essentially “zero”—in the nA range—current in its continuously active state. Moreover, because, except for a short time at power-up when a RESET pulse is generated, the POR circuit consumes zero or substantially zero current, it would be desirable to provide a POR circuit that does not rely on a PD input to activate. Finally, it would be desirable to provide a zero current POR circuit that can be left in a powered-up state at all times, since its default state, which is only entered for a very short time after generating a RESET pulse at power-up, consumes zero or substantially zero current.